1. Field of the Invention
The present invention relates to a processor system which includes a processor having a function for writing back data stored in a cache memory to an external memory. Especially, the present invention relates to a processor system capable of performing DMA transfer from an I/O circuit to the external memory.
2. Related Background Art
Operation frequency of a processor tends to increase year by year. However, an external memory used for a main memory is not faster than the processor. Because of this, a cache memory is generally used to infill a difference of speed between the processor and the external memory.
The cache memory sends and receives data in regard to the external memory for each cache line formed of a plurality of words. In the case of a system having the cache memory called as a write-back cache, data written into the cache memory by the processor has to be written back to the external memory. Because of this, a dirty bit indicating whether or not the data has been written back to the external memory is provided for each cache line. When the dirty bit is set, it is indicated that the write-back to the external memory is not yet finished.
Various I/O circuits are connected to the processor. When data is transferred by the DMA (Direct Memory Access) transfer between each I/O circuit and the external memory without passing through the processor, the processing burden of the processor is reduced, and it is possible to transfer data from the I/O circuit to the external memory at high latency.
However, the DMA transfer in which data is transferred from the external memory to the I/O circuits and the copy of this data in the cache memory is dirty may be instructed. In such a case, before a performing the DMA transfer, the write-back operation has to be performed in regard to the external memory. Furthermore, when the DMA transfer is performed in regard to the address range including the address of the cache line to which the write-back operation is not yet performed, it is necessary to invalidate the cache line. Otherwise, if the dirty bit of the cache line is set, it is necessary to perform the write-back operation and then to invalidate the cache line.
For example, FIG. 8 shows an example in which “0x2000” is stored in the tag for storing the address information of the cache memory and a certain cache line is formed of four words. In this case, four words data from 0x2000 to 0x200f is stored in the cache line.
In the case of FIG. 8, even if only a portion of the cache line is updated, the dirty bit of the cache line is set. That is, it is impossible to know the updated location of the cache line.
When the dirty bit is set, and for example, one word data from address 0x2004 is transferred by DMA from the I/O circuit to the external memory, the write-back operation of the cache line is first performed before the DMA transfer.
However, when only one byte of address 0x2005 is updated in the cache line, this one byte is rewritten by the DMA transfer. Because of this, the write-back operation becomes meaningless.
Thus, although the conventional processor system has dirty bits in units of the cache line, it has no information indicating the updated location in the cache line. Because of this, despite being practically unnecessary, the write-back operation may be performed, thereby causing the unnecessary bus transaction.
Furthermore, in order to avoid occurrence of such an unnecessary bus transaction, a method of changing data declaration so that data is arranged one by one when defining data as a target of DMA may be adopted. The method is that, for example, dummy declaration is inserted between data declarations. Such a method causes development efficiency of software to lower.
On the other hand, in the case of the processor having a snoop function for detecting whether or not to hold newest data in the cache memory to be stored in the external memory, the operation for maintaining data consistency by software is unnecessary. In the case of performing the DMA transfer from the I/O circuit to the external memory, the following operation is performed by hardware.
When the cache-hit of the subject for the DMA transfer occurs, the cache line is invalidated. When the dirty bit is set to the cache line, the cache line is written back before performing the DMA transfer, and then the DMA transfer is performed.
Even in this case, for example, when address 0x2000 is stored in the tag and the dirty bit is set, even if data to be updated exists in only the address 0x2005, the entire cache line is written back.
Thus, because the conventional processor having the snoop function did not have the information indicating the updated location in the cache line, the write-back operation is necessary, thereby occurring the unnecessary bus transaction.
Furthermore, when the method for changing the data declaration by software is adopted, there was a problem in which the development efficiency of software deteriorates.